The invention relates to a method of manufacturing a semiconductor device with a semiconductor body of silicon comprising at least an insulated gate field effect transistor in which a silicon oxide layer is provided on the surface of the silicon body, on which oxide layer a doped silicon layer is provided, after which the silicon layer is provided with a masking layer and the masking layer and the underlying silicon layer are etched into a pattern comprising at least a gate electrode, and nitrogen ions are then implanted in the parts of the silicon surface not underlying the silicon layer, after which the exposed parts of the silicon pattern are thermally oxidized and source and drain zones are then formed by ion implantation in parts of the silicon surface not underlying the silicon pattern.
A method of the kind described above is known from Netherlands Patent Application No. 7902878 (laid open to public inspection).
Various methods have been developed for the self-registering manufacture of insulated gate field effect transistors, all of which method have in common that the gate electrode, either with or without the mask used for its formation is used as a doping mask in doping the source and drain zones. The gate electrode usually consists of polycrystalline silicon, and in order to prevent shortcircuits between the gate electrode and the source and drain zones, at least the edge of the gate electrode must be covered with an insulating layer, for example by thermal oxidation. To prevent difficulties in doping the source and drain zones and in forming contact windows on said zones, it is desirable that during the thermal oxidation of the gate electrode the parts of the silicon surface not underlying the gate electrode should be protected against oxidation.
According to a first method described in U.S. Pat. No. 3,843,216 this may be done by covering the silicon surface, prior to providing the gate electrode of polycrystalline silicon, with a silicon nitride-containing layer masking against oxidation, on which layer the gate electrode is provided, after which the whole gate electrode is covered with a thermal oxide layer. One of the disadvantages of this method, however, is that the dielectric below the gate electrode comprises silicon nitride, which may sometimes give rise to instabilities and to further undesired effects.
Therefore a second method has been developed as described in the above-mentioned Netherlands Patent Application No. 7902878. In this method no silicon nitride layer is used but nitrogen ions are implanted in the surface regions destined for the source and drain zones, the gate electrode being masked against said implantation. In the subsequent thermal oxidation in which the gate electrode is entirely covered with an oxide layer, the parts of the silicon surface implanted with nitrogen ions and present beside the gate elctrode are protected against oxidation.
For the self-registering manufacture of field effect transistors of very small dimensions in monolithic integrated circuits of large packing density, neither of these methods provides a satisfactory solution. First of all, in order not to run the risk of the polycrystalline silicon being oxidized through entirely, the thermal oxidation must be very readily controlled and the silicon layer must be comparatively thick. However, such thick layers are difficult to etch very narrowly in a reproducible manner. On the other hand, the oxide on the gate electrode must not be too thin either. A deposited polycrystalline silicon layer has a rough surface and an oxide layer grown thereon, when it is too thin, shows defects ("pin holes") so that shortcircuits with, for example, a metallization may occur.
However, a thick oxide layer on the gate electrode has an important disadvantage. In fact, in order to determine the threshold voltage, an ion implantation in the channel region is usually necessary. In the case of field effect transistors of very small dimensions said implantation will preferably be carried out as late as possible so as to minimize the number of subsequent heating steps which may result in an undesired further diffusion of the doping atoms already present. Therefore this implantation will preferably be carried out after the provision of the gate electrode and through the gate electrode. In the presence of a thick oxide layer on the gate electrode, however, this is substantially impossible. Finally, the presence of thick silicon layers and silicon oxide layers may present problems with respect to the "stepcoating" by further insulating layers provided subsequently so that inter alia a metal track which crosses the gate electrode or the interconnection paths belonging to the silicon pattern may be interrupted.